Conventionally, there has been proposed a wafer level package structure. For example, JP-2005-251898A discloses a structure including a first substrate having a first sealing metal layer disposed around an element and a second substrate having a second sealing metal layer that is located facing the first sealing metal layer. In the structure, the first and second metal layers are joined together through a third conductor so that the element in the first substrate can be hermetically sealed between the first and second substrates.
The structure is obtained by joining a wafer-shaped first substrate and a wafer-shaped second substrate together through a third conductor to form a stacked wafer and by dicing (i.e., cutting) the stacked wafer into individual chips.
In the structure, the substrates are joined together only through the third conductor joined to the sealing metal layers. When force is applied to the substrates during a dicing process, a bonding force between each substrate and the metal layer and a bonding force between the third conductor and each metal layer may be weakened. As a result, the substrate and each metal layer may be separated from each other, and the third conductor and each metal layer may be separated from each other.
Further, after the stacked wafer is diced into individual chips, each chip may be subjected to external force that can weaken the bonding force between the sealing metal layer and each portion. As a result, the separation between the sealing metal layer and each portion may occur.